Services
Full-flow VLSI engineering, delivered by people who have shipped silicon.
Whether you need a single staff engineer or an entire design center, every VelSil engagement is led by senior architects with multiple production tape-outs under their belt.
01
Front-end Design
- SoC & IP architecture
- RTL design (Verilog/SystemVerilog)
- Microarchitecture spec
- Low-power design (UPF)
- Synthesis & STA
02
Verification
- UVM testbench development
- Formal verification
- Emulation (Palladium/Veloce)
- FPGA prototyping
- Coverage closure
03
Physical Design
- Floorplan & power planning
- Place & route
- Clock tree synthesis
- Timing & signoff
- DRC/LVS to GDSII
04
DFT
- Scan insertion
- MBIST / LBIST
- ATPG pattern generation
- JTAG / IEEE 1500
- Silicon debug
05
Analog & Mixed-Signal
- PLL / DLL design
- SerDes & high-speed I/O
- ADC / DAC
- Custom layout
- Analog verification
06
Post-Silicon & Embedded
- Lab bring-up
- Firmware / drivers
- Validation engineering
- Characterization
- Yield analysis
Need a custom scope?
We staff and manage entire design programs end-to-end.